Add MTL support

intel · Aug 18, 2022 · 2013a0c · 2013a0c
1 parent 9d9b824
commit 2013a0c
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Showing 13 changed files with 65 additions and 21 deletions.
diff --git a/IGC/AdaptorCommon/RayTracing/PrologueShaders.cpp b/IGC/AdaptorCommon/RayTracing/PrologueShaders.cpp
@@ -35,6 +35,7 @@ namespace IGC {
         {
         case IGFX_DG2:
         case IGFX_PVC:
+        case IGFX_METEORLAKE:
             pKernel = (void*)prologueShader_XeHP;
             size    = sizeof(prologueShader_XeHP);
             break;

diff --git a/IGC/Compiler/CISACodeGen/CISABuilder.cpp b/IGC/Compiler/CISACodeGen/CISABuilder.cpp
@@ -3139,6 +3139,10 @@ namespace IGC
             {
                 return Xe_DG2;
             }
+            else if (platform->getPlatformInfo().eProductFamily == IGFX_METEORLAKE)
+            {
+                return Xe_MTL;
+            }
             else if (platform->getPlatformInfo().eProductFamily == IGFX_PVC)
             {
                 if (platform->getPlatformInfo().usRevId >= REVISION_B)

diff --git a/IGC/Compiler/CISACodeGen/DriverInfo.hpp b/IGC/Compiler/CISACodeGen/DriverInfo.hpp
@@ -353,7 +353,7 @@ namespace IGC
         virtual bool EnableLSCForLdRawAndStoreRawOnDG2() const { return false; }
         // Check SLM limit on compute shader to select SIMD8
         virtual bool SupportCSSLMLimit() const { return false; }
-
+        virtual bool supportsSIMD32forCPS() const { return true; }
 
         // When dual-source blending is enabled, enable sending the
         // single-source RTW message (with data for the second color) after the

diff --git a/IGC/Compiler/CISACodeGen/EmitVISAPass.cpp b/IGC/Compiler/CISACodeGen/EmitVISAPass.cpp
@@ -712,7 +712,8 @@ bool EmitPass::runOnFunction(llvm::Function& F)
             }
             if ((IGC_GET_FLAG_VALUE(CodePatchFilter) & (0x1 << 0x4)) &&
                 (m_pCtx->platform.getPlatformInfo().eProductFamily == IGFX_DG2 ||
-                    m_pCtx->platform.getPlatformInfo().eProductFamily == IGFX_ALDERLAKE_P)) {
+                 m_pCtx->platform.getPlatformInfo().eProductFamily == IGFX_ALDERLAKE_P ||
+                 m_pCtx->platform.getPlatformInfo().eProductFamily == IGFX_METEORLAKE)) {
                 m_encoder->SetIsCodePatchCandidate(false);
             }
         }
@@ -6669,6 +6670,7 @@ void EmitPass::emitSampleInstruction(SampleIntrinsic* inst)
 
     bool cpsEnable =
         false;
+    cpsEnable &= m_SimdMode != SIMDMode::SIMD32;
 
     SmallVector<CVariable*, 4>  payload;
 
@@ -13703,7 +13705,7 @@ void EmitPass::emitMemoryFence(llvm::Instruction* inst)
         // When post-atomic fence is added with L1 invalidate, we may want to limit the scope to subslice.
         if (Force_Local_LSC_Scope)
             scope = (sfid == LSC_SLM) ? LSC_SCOPE_GROUP : LSC_SCOPE_LOCAL;
-        // Change the scope from `GPU` to `Tile` on single-tile platforms to avoid L3 flush on DG2
+        // Change the scope from `GPU` to `Tile` on single-tile platforms to avoid L3 flush on DG2 and MTL
         if (scope == LSC_SCOPE_GPU &&
             !m_currShader->m_Platform->hasMultiTile() &&
             m_currShader->m_Platform->hasL3FlushOnGPUScopeInvalidate() &&
@@ -19178,7 +19180,8 @@ EmitPass::LscMessageFragmentInfo EmitPass::checkForLscMessageFragmentation(
     const int dataSizeRegBytes = toBytesGrf(dataSize);
     const int dataSizeMemBytes = toBytesMem(dataSize);
     // const int dataElemsCount = toCount(dataElems);
-    const bool isDg2 = m_currShader->m_Platform->getPlatformInfo().eProductFamily == IGFX_DG2;
+    const bool isDg2 = (m_currShader->m_Platform->getPlatformInfo().eProductFamily == IGFX_DG2
+        || m_currShader->m_Platform->getPlatformInfo().eProductFamily == IGFX_METEORLAKE);
     const bool isPvcPlus = !isDg2;
     const int simdElems = numLanes(m_currShader->m_SIMDSize);
     bool halfSimdMode =
@@ -19719,7 +19722,7 @@ void EmitPass::emitLSCFence(llvm::GenIntrinsicInst* inst)
     {
         flushType = LSC_FENCE_OP_INVALIDATE;
     }
-    // Change the scope from `GPU` to `Tile` on single-tile platforms to avoid L3 flush on DG2
+    // Change the scope from `GPU` to `Tile` on single-tile platforms to avoid L3 flush on DG2 and MTL
     if (scope == LSC_SCOPE_GPU &&
         !m_currShader->m_Platform->hasMultiTile() &&
         m_currShader->m_Platform->hasL3FlushOnGPUScopeInvalidate() &&
@@ -19901,7 +19904,8 @@ void EmitPass::emitSyncStackID(llvm::GenIntrinsicInst* I)
     constexpr uint32_t ssid_bit_loc = 8;
     constexpr uint32_t ssid_mask = BIT(ssid_bit_loc);
 
-    if (m_currShader->m_Platform->getPlatformInfo().eProductFamily == IGFX_DG2)
+    if (m_currShader->m_Platform->getPlatformInfo().eProductFamily == IGFX_DG2 ||
+        m_currShader->m_Platform->getPlatformInfo().eProductFamily == IGFX_METEORLAKE)
     {
         euid_offset = 7;
         euid_and_imm = BITMASK_RANGE(4, 7);

diff --git a/IGC/Compiler/CISACodeGen/Platform.hpp b/IGC/Compiler/CISACodeGen/Platform.hpp
@@ -313,6 +313,10 @@ bool SupportCPS() const
 {
     return (m_platformInfo.eRenderCoreFamily >= IGFX_GEN10_CORE);
 }
+bool supportsSIMD32forCPS() const
+{
+    return (m_platformInfo.eProductFamily >= IGFX_METEORLAKE);
+}
 
 bool supportsThreadCombining() const
 {
@@ -497,7 +501,7 @@ bool supportBfnInstruction() const
 
 bool supportDpasInstruction() const
 {
-    return isProductChildOf(IGFX_XE_HP_SDV);
+    return isProductChildOf(IGFX_XE_HP_SDV) && m_platformInfo.eProductFamily != IGFX_METEORLAKE;
 }
 
 bool hasPackedRestrictedFloatVector() const
@@ -660,7 +664,8 @@ bool hasHalfSIMDLSC() const
         GFX_IS_DG2_G11_CONFIG(m_platformInfo.usDeviceID) ||
         GFX_IS_DG2_G12_CONFIG(m_platformInfo.usDeviceID) ||
         // false for PVC XL A0 RevID==0x0, true from PVC XT A0 RevID==0x3==REVISION_B
-        (m_platformInfo.eProductFamily == IGFX_PVC && m_platformInfo.usRevId >= REVISION_B);
+        (m_platformInfo.eProductFamily == IGFX_PVC && m_platformInfo.usRevId >= REVISION_B) ||
+        m_platformInfo.eProductFamily == IGFX_METEORLAKE;
 }
 
 bool NeedsLSCFenceUGMBeforeEOT() const
@@ -749,7 +754,8 @@ bool supports3DAndCubeSampleD() const
     // Make sure to match hasSupportForSampleDOnCubeTextures LLVM3DBuilder\BuiltinsFrontend.hpp
     return (
         m_platformInfo.eProductFamily != IGFX_XE_HP_SDV &&
-        m_platformInfo.eProductFamily != IGFX_DG2
+        m_platformInfo.eProductFamily != IGFX_DG2 &&
+        m_platformInfo.eProductFamily != IGFX_METEORLAKE
         ) ||
         IGC_IS_FLAG_DISABLED(EnableSampleDEmulation);
 }
@@ -799,7 +805,8 @@ uint32_t getMaxLSCBlockMsgSize(bool isD64 = true) const
 
 bool hasURBFence() const
 {
-    return m_platformInfo.eProductFamily == IGFX_DG2;
+    return m_platformInfo.eProductFamily == IGFX_DG2 ||
+        m_platformInfo.eProductFamily == IGFX_METEORLAKE;
 }
 
 bool hasMultiTile() const
@@ -811,7 +818,8 @@ bool hasMultiTile() const
 // UGM LSC fence with GPU scope triggers L3 flush
 bool hasL3FlushOnGPUScopeInvalidate() const
 {
-    return m_platformInfo.eProductFamily == IGFX_DG2;
+    return m_platformInfo.eProductFamily == IGFX_METEORLAKE ||
+           m_platformInfo.eProductFamily == IGFX_DG2;
 }
 
 bool L3CacheCoherentCrossTiles() const {
@@ -821,6 +829,7 @@ bool L3CacheCoherentCrossTiles() const {
 bool AllowFenceOpt() const
 {
     return ((m_platformInfo.eProductFamily == IGFX_DG2
+        || m_platformInfo.eProductFamily == IGFX_METEORLAKE
         || m_platformInfo.eProductFamily == IGFX_PVC) &&
         IGC_IS_FLAG_ENABLED(EnablePlatformFenceOpt));
 }
@@ -897,7 +906,8 @@ bool typedReadSupportsAllRenderableFormats() const
 
     if ((m_platformInfo.eProductFamily == IGFX_DG2 && isChildOfDG2C0) ||
         (m_platformInfo.eProductFamily == IGFX_DG2 && isDG2G11Config && isChildOfDG2B0) ||
-        (m_platformInfo.eProductFamily == IGFX_DG2 && isDG2G12Config ) ||
+        (m_platformInfo.eProductFamily == IGFX_DG2 && isDG2G12Config) ||
+        (m_platformInfo.eProductFamily == IGFX_METEORLAKE) ||
         (m_platformInfo.eRenderCoreFamily == IGFX_XE_HPC_CORE))
     {
         return IGC_IS_FLAG_DISABLED(ForceFormatConversionDG2Plus);
@@ -908,7 +918,8 @@ bool typedReadSupportsAllRenderableFormats() const
 
 bool needsWAForThreadsUtilization() const
 {
-    return m_platformInfo.eProductFamily == IGFX_DG2;
+    return m_platformInfo.eProductFamily == IGFX_DG2 ||
+           m_platformInfo.eProductFamily == IGFX_METEORLAKE;
 }
 
 bool supportDualSimd8PS() const
@@ -1013,7 +1024,8 @@ bool supportAIParameterCombiningWithLODBiasEnabled() const
     return IGC_IS_FLAG_ENABLED(EnableAIParameterCombiningWithLODBias) &&
            (m_platformInfo.eProductFamily == IGFX_DG2 && SI_WA_FROM(m_platformInfo.usRevId, ACM_G10_GT_REV_ID_B0)) ||
            GFX_IS_DG2_G12_CONFIG(m_platformInfo.usDeviceID) ||
-           GFX_IS_DG2_G11_CONFIG(m_platformInfo.usDeviceID);
+           GFX_IS_DG2_G11_CONFIG(m_platformInfo.usDeviceID) ||
+            m_platformInfo.eProductFamily == IGFX_METEORLAKE;
 }
 
 bool useScratchSpaceForOCL() const
@@ -1071,7 +1083,8 @@ bool hasNoInt64Inst() const {
         m_platformInfo.eProductFamily == IGFX_ALDERLAKE_P ||
         m_platformInfo.eProductFamily == IGFX_ALDERLAKE_N ||
         m_platformInfo.eProductFamily == IGFX_DG1 ||
-        m_platformInfo.eProductFamily == IGFX_DG2;
+        m_platformInfo.eProductFamily == IGFX_DG2 ||
+        m_platformInfo.eProductFamily == IGFX_METEORLAKE;
 }
 
 //all the platforms which DONOT support 64 bit float operations
@@ -1100,7 +1113,13 @@ bool hasCorrectlyRoundedMacros() const {
         m_platformInfo.eProductFamily != IGFX_ALDERLAKE_S &&
         m_platformInfo.eProductFamily != IGFX_ALDERLAKE_P &&
         m_platformInfo.eProductFamily != IGFX_ALDERLAKE_N &&
-        m_platformInfo.eProductFamily != IGFX_DG2;
+        m_platformInfo.eProductFamily != IGFX_DG2 &&
+        m_platformInfo.eProductFamily != IGFX_METEORLAKE;
+}
+
+// Has 64bit support but use 32bit for perf reasons
+bool preferFP32Emu() const {
+    return m_platformInfo.eProductFamily == IGFX_METEORLAKE;
 }
 
 bool supportMixMode() const {
@@ -1119,7 +1138,8 @@ bool NeedsHDCFenceBeforeEOTInPixelShader() const
 
 bool canFuseTypedWrite() const
 {
-    return false;
+    return (IGC_IS_FLAG_ENABLED(FuseTypedWrite) &&
+            m_platformInfo.eProductFamily == IGFX_METEORLAKE);
 }
 
 bool enableSetDefaultTileYWalk() const
@@ -1237,7 +1257,8 @@ bool WaDisablePrimitiveReplicationWithCPS() const
 bool supportSystemFence() const
 {
     return hasLSC()
-        && m_platformInfo.eProductFamily != IGFX_DG2;
+        && m_platformInfo.eProductFamily != IGFX_DG2
+        && m_platformInfo.eProductFamily != IGFX_METEORLAKE;
 }
 
 

diff --git a/IGC/Compiler/CISACodeGen/ShaderCodeGen.cpp b/IGC/Compiler/CISACodeGen/ShaderCodeGen.cpp
@@ -447,7 +447,11 @@ void AddLegalizationPasses(CodeGenContext& ctx, IGCPassManager& mpm, PSSignature
         ((IGC_IS_FLAG_ENABLED(ForceSPDivEmulation) ||
             (ctx.m_DriverInfo.NeedIEEESPDiv() && !ctx.platform.hasCorrectlyRoundedMacros()))
         ? EmuKind::EMU_SP_DIV : 0);
-    if (ctx.platform.Enable32BitIntDivRemEmu())
+    if (ctx.platform.preferFP32Emu() && IGC_IS_FLAG_DISABLED(Force32BitIntDivRemEmu)) {
+        // Prefer using FP32 emulation even though DP support is available
+        theEmuKind |= EmuKind::EMU_I32DIVREM_SP;
+    }
+    else if (ctx.platform.Enable32BitIntDivRemEmu())
     {
         if (!ctx.platform.hasNoFP64Inst())
         {

diff --git a/IGC/Compiler/Optimizer/OpenCLPasses/LSCFuncs/LSCFuncsResolution.cpp b/IGC/Compiler/Optimizer/OpenCLPasses/LSCFuncs/LSCFuncsResolution.cpp
@@ -215,6 +215,7 @@ bool LSCFuncsResolution::runOnFunction(Function &F)
     switch (m_pCtx->platform.getPlatformInfo().eProductFamily)
     {
     case IGFX_DG2:
+    case IGFX_METEORLAKE:
         defaultSimdSize = 16;
         break;
     default:

diff --git a/IGC/Compiler/igc_workaround.cpp b/IGC/Compiler/igc_workaround.cpp
@@ -145,6 +145,8 @@ namespace IGC
             if (IGC_IS_FLAG_ENABLED(Enable_Wa22010493955))
                 waTable.Wa_22010493955 = 1;
 
+            break;
+        case IGFX_METEORLAKE:
             break;
         default:
             IGC_ASSERT(0);

diff --git a/IGC/LLVM3DBuilder/BuiltinsFrontend.hpp b/IGC/LLVM3DBuilder/BuiltinsFrontend.hpp
@@ -56,7 +56,8 @@ inline bool genplatform::hasSupportForAllOCLImageFormats() const
     bool isDG2G11EUConfig = GFX_IS_DG2_G11_CONFIG(m_platformInfo->usDeviceID);
     bool isDG2G12EUConfig = GFX_IS_DG2_G12_CONFIG(m_platformInfo->usDeviceID);
     if ((m_platformInfo->eProductFamily == IGFX_DG2 && isDG2C0Plus) ||
-        (m_platformInfo->eProductFamily == IGFX_DG2 && isDG2G11EUConfig && isDG2B0Plus))
+        (m_platformInfo->eProductFamily == IGFX_DG2 && isDG2G11EUConfig && isDG2B0Plus) ||
+        (m_platformInfo->eProductFamily == IGFX_METEORLAKE))
     {
         return true;
     }

diff --git a/IGC/common/SystemThread.cpp b/IGC/common/SystemThread.cpp
@@ -930,6 +930,7 @@ CGenSystemInstructionKernelProgram* CGenSystemInstructionKernelProgram::Create(
                 SIPIndex = bindlessMode ? XE_HP_CSR_DEBUG_BINDLESS : XE_HP_CSR_DEBUG;
                 break;
             case IGFX_DG2:
+            case IGFX_METEORLAKE:
                 SIPIndex =  bindlessMode ? XE_HPG_CSR_DEBUG_BINDLESS : XE_HPG_CSR_DEBUG;
                 break;
       // No support for Bindful mode for PVC.
@@ -960,6 +961,7 @@ CGenSystemInstructionKernelProgram* CGenSystemInstructionKernelProgram::Create(
                 SIPIndex = XE_HP_CSR;
             case IGFX_DG2:
             case IGFX_PVC:
+            case IGFX_METEORLAKE:
 
             default:
                 break;

diff --git a/IGC/common/VCPlatformSelector.hpp b/IGC/common/VCPlatformSelector.hpp
@@ -56,7 +56,9 @@ inline const char *getPlatformStr(PLATFORM Platform, unsigned &RevId) {
     else if (Product == IGFX_XE_HP_SDV)
       return "XEHP";
     else if (Product == IGFX_DG2)
-      return "DG2";
+        return "DG2";
+    else if (Product == IGFX_METEORLAKE)
+        return "MTL";
     else if (Product == IGFX_PVC) {
       // fixing revision id for PVC to compute tile
       RevId &= cmc::ComputeTileMaskPVC;

diff --git a/IGC/common/igc_flags.h b/IGC/common/igc_flags.h
@@ -411,6 +411,7 @@ DECLARE_IGC_REGKEY(bool, Enable64BitEmulationOnSelectedPlatform, true, "Enable 6
 DECLARE_IGC_REGKEY(DWORD, EnableConstIntDivReduction,   0x1,   "Enables strength reduction on integer division/remainder with constant divisors/moduli", true)
 DECLARE_IGC_REGKEY(DWORD, EnableIntDivRemCombine,       0x0,   "Given div/rem pairs with same operands merged; replace rem with mul+sub on quotient; 0x3 (set bit[1]) forces this on constant power of two divisors as well", true)
 DECLARE_IGC_REGKEY(bool, EnableHFpacking,               false, "Enable HF packing", false)
+DECLARE_IGC_REGKEY(bool, Force32BitIntDivRemEmu, false, "Force 32-bit Int Div/Rem emulation using fp64, ignored if no native fp64 support", true)
 DECLARE_IGC_REGKEY(bool, EnableWideMulMad,              false, "Enable wide (64-bit) mul and mad instructions", false)
 DECLARE_IGC_REGKEY(bool, EnableRecursionOpenCL,         true,  "Enable recursion with OpenCL user functions", false)
 DECLARE_IGC_REGKEY(bool, ForceDPEmulation,              false, "Force double emulation for testing purpose", false)

diff --git a/inc/common/igfxfmid.h b/inc/common/igfxfmid.h
@@ -36,6 +36,7 @@ typedef enum {
     IGFX_XE_HP_SDV = 1250,
     IGFX_DG2 = 1270, // aka - ACM/Alchemist
     IGFX_PVC = 1271,
+    IGFX_METEORLAKE = 1272,
     IGFX_MAX_PRODUCT,